We have blogged about the benefits of the AC field Hall measurement method to characterize low-mobility materials. But even when mobilities aren’t very low, the AC method offers an advantage over the traditional DC method namely when very small Hall voltages are involved.
An example of this can be seen in a paper recently published in the Beilstein Journal of Nanotechnology. It describes work of scientists from Ireland’s Tyndall National Institute experimenting with phosphorus monolayer doping (MLD) of silicon on insulator (SOI) substrates with nanoscale dimensions (sub-66 nm silicon layer). Their research is like that of others who are aiming to shrink the size of transistors and push the limits of Moore’s Law.
For their work, the Tyndall Institute researchers used a Lake Shore 8404 HMS system with an AC field Hall option to help characterize samples having undergone different processing methods for doping of the SOI substrate. As a result, they found that carrier concentration values increased when doped SOI samples were scaled from 66 to 13 nm in silicon layer thickness. The mobilities exhibited weren’t at all low, so AC field Hall provided no advantage over the DC method for measuring Hall mobility. However, because the samples exhibited high carrier concentrations and the Hall voltages were intrinsically small—on the order of 25 µV—the AC field Hall method proved advantageous because it was demonstratively better at measuring these smaller voltages (see Table S1 of the supplementary data).